// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module ClkDivTree
(
//% Clock
input   i_Clk,
//% Reset
input   i_Rst_n,
//% 1uS Clock enable
output  o_1uSCE,
//% 5uS Clock enable
output  o_5uSCE,
//% 10uS Clock enable
output  o_10uSCE,
//% 50uS Clock enable
output  o_50uSCE,
//% 500uS Clock enable
output  o_500uSCE,
//% 1mS Clock enable
output  o_1mSCE,
//% 20mS Clock enable
output  o_20mSCE,
//% 250mS Clock enable
output  o_250mSCE,
//% 1SCE Clock Enable
output  o_1SCE
);  

wire w1uSCE;
wire w5uSCE;
wire w10uSCE;
wire w50uSCE;
wire w500uSCE;
wire w1mSCE;
wire w250mSCE;
wire w20mSCE;
wire w1SCE;

assign  o_1uSCE      =   w1uSCE;
assign  o_5uSCE      =   w5uSCE;
assign  o_10uSCE     =   w10uSCE;
assign  o_50uSCE     =   w50uSCE;
assign  o_500uSCE    =   w500uSCE;
assign  o_1mSCE      =   w1mSCE;
assign  o_250mSCE    =   w250mSCE;
assign  o_20mSCE     =   w20mSCE;
assign  o_1SCE       =   w1SCE;

//
//% 1uS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS ( 1 ),
    .MAX_DIV_CNT  ( 1 )
)m1uSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( 1'b1 ),
    .o_DivClk            ( w1uSCE )
);

//
//% 5uS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS ( 3 ),
    .MAX_DIV_CNT  ( 4 )
)m5uSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w1uSCE ),
    .o_DivClk            ( w5uSCE )
);

//
//% 10uS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS ( 4 ),
    .MAX_DIV_CNT  ( 9 )
)m10uSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w1uSCE ),
    .o_DivClk            ( w10uSCE )
);
//
//% 50uS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS ( 3 ),
    .MAX_DIV_CNT  ( 4 )
)m50uSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w10uSCE ),
    .o_DivClk            ( w50uSCE )
);
//
//% 500uS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS       ( 4 ),
    .MAX_DIV_CNT        ( 9 )
)m500uSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w50uSCE ),
    .o_DivClk            ( w500uSCE )
);  
//
//% 1mS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS       ( 1 ),
    .MAX_DIV_CNT        ( 1 )
)m1mSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w500uSCE ),
    .o_DivClk            ( w1mSCE )
);  
//
//% 250mS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS       ( 4 ),
    .MAX_DIV_CNT        ( 11 )
)m250mSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w20mSCE ),
    .o_DivClk            ( w250mSCE )
);

//
//% 1S Clock divide
//

Clkdiv #
(
    .MAX_DIV_BITS       ( 3 ),
    .MAX_DIV_CNT        ( 4 )
)m1SCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w250mSCE ),
    .o_DivClk            ( w1SCE )
);
//
//% 20mS Clock divide
//
Clkdiv #
(
    .MAX_DIV_BITS       ( 5 ),
    .MAX_DIV_CNT        ( 19 )
)m20mSCE
(
    .i_Clk               ( i_Clk ),
    .i_Rst_n             ( i_Rst_n ),
    .i_CE                ( w1mSCE ),
    .o_DivClk            ( w20mSCE )
);

endmodule
